μNet: Ultra-Low-Memory and Low-Complexity Speech Enhancement for Embedded Digital Signal Processors
Shrishti Saha Shetu, Jose Miguel Martinez Aponte, Nagashree K. S. Rao, Sharvin Vittappan, Oliver Thiergart, Emanuël A. P. Habets,
International Audio Laboratories Erlangen, Am Wolfsmantel 33, 91058 Erlangen, Germany
{shrishti.saha.shetu}@iis.fraunhofer.de
Abstract
Speech enhancement on embedded digital signal processors (DSPs) imposes strict constraints on memory footprint, computational complexity, latency, and support for integer operations. Although recent DNN-based approaches have
addressed these challenges individually, no unified framework in the literature simultaneously addresses all these requirements for practical deployment. In this work, we propose μNet, an ultra-low-memory, low-complexity, and low-latency end-to-end DNN model. The proposed method requires only 90 KB of static memory and 28 MMACs, while supporting an algorithmic latency
as low as 4 ms with performance comparable to state-of-the-art methods of similar complexity. Our experiments demonstrate that μNet is compatible with neural accelerators and supports full integer-arithmetic operations on consumer DSP platforms such as Cadence Tensilica HiFi 4/5.
Evaluation Scenarios
In our work, we evaluate our proposed methods in different evaluation scenario against the baselines methods.
1. Baseline comparision
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2. Low Latency results
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